Low-Dropout Voltage Regulator Designed with Nanowire TFET with Different Source Composition Experimental Data

This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and MOSFET. The devices are mod-eled lookup tables implemented with experimental measures TFETs different source compositions (Si, SiGe Ge) In order to compare designs, transistors differential amplifier in all LDOs is biased gm/ID = 8 V-1 a load 1 μA 10-pF. It shown that TFET based stables without need compensator capacitor (CC) even for higher capacitance. For MOSFET LDO, CC 5-pF was used. study shows deliver effi-ciency due possibility operate low bias current. transient analysis it have lower overshoot but delay. Ge-TFET LDO pre-sented settling times line close 15 μs 30 μs. SiGe-TFET best loop gain (60 dB), while Si-TFET deliv-ers lowest quiescent current (300 pA) GBW (70 KHz) PSR (-52 dB). concluded can specifications similar or bet-ter than less power consumption.